The present invention relates to a nonvolatile semiconductor memory device and a method for fabricating the same, and also relates to a semiconductor integrated circuit device.
In memories for portable units and memory-incorporated logic VLSI's, the technologies for nonvolatile memories have become increasingly important because it is demanded to reduce the costs per bit and to enhance electrical rewrite functions. For such purposes, various structures and fabrication processes have been suggested.
Hereinafter, conventional nonvolatile memories will be described while giving the outlines of such structures and processes.
FIG. 23 shows the cross section of a nonvolatile semiconductor memory device having a so-called "split-gate type" structure. Such a device was suggested by G. Samchisa et al. in IEEE J. Solid-State Circuits, pp. 676, 1987.
In the device shown in FIG. 23, a tunnel oxide film 102, a floating gate 103 and a capacitive insulating film 104 are formed on the upper surface of a semiconductor substrate 101. A control gate 105 is further formed so as to cover the floating gate 103. Also, in the semiconductor substrate 101, a source region 106, which have been doped with an impurity at a high concentration, is formed in a region partially overlapping with the control gate 105, and a drain region 107, which have been doped with an impurity at a high concentration, is formed in a region partially overlapping with the floating gate 103.
The device shown in FIG. 23 has a so-called "split-gate structure" in which the control gate 105 and the floating gate 103 are disposed via the capacitive insulating film over a channel region between the source region 106 and the drain region 107. The floating gate 103 functions as a node in which information is stored and the charged states thereof are made to correspond to "0" and "1" of the information. By utilizing the fact that the threshold voltage as viewed from the control gate 105 is varied in accordance with the amount of charge accumulated in the floating gate 103, the reading of data is performed.
The writing of data utilizes a strong lateral high electric field, which is generated in a boundary between a "drain potential expansion region" in a region immediately under the floating gate 103 and an "inversion channel region" in a region immediately under the control gate 105. By utilizing the phenomenon that channel hot electrons, which have obtained high energy as a result of the acceleration caused by the lateral high electric field, are injected into the oxide film so as to reach the floating gate 103, a relatively high electron injection efficiency is achieved. Such an electron injection is called a "source-side injection".
The erasure of data is performed by taking out the electrons in the floating gate 103 into the drain region 107 by the use of a Fowler-Nordheim (FN) tunneling phenomenon. In order to utilize the FN tunneling phenomenon, a high electric field of about 10.5 MV/cm to about 11 MV/cm is required to be formed in the oxide film 102. Since the tunnel oxide film 102 of the device of the above-cited document is as thick as 20 nm, a high voltage of about 21 V is applied to the drain region 107 when data is erased.
Since the structure shown in FIG. 23 uses the drain region 107 in both cases of writing and erasing data, the compatibility between the operating speed and the reliability is insufficient.
In order to make the operating speed and the reliability compatible, a device shown in FIG. 24 has been proposed. This device was disclosed by S. Kianian et al. in IEEE Symposium VLSI Technology 1994, Digest of Technical Papers, pp. 71.
In the device shown in FIG. 24, a gate oxide film 204, a floating gate 203 and a control gate 205 partially overlapping with the floating gate 203 are formed over a semiconductor substrate 201. In the semiconductor substrate 201, an extremely thick source region 206, which have been doped with an impurity at a high concentration, is formed in a region partially overlapping with the floating gate 203, and a drain region 207, which have been doped with an impurity at a high concentration, is formed in a region partially overlapping with the control gate 205. And the control gate 205 and the floating gate 203 are disposed via a tunnel oxide film 202 over a channel region between the source region 206 and the drain region 207.
The writing of data utilizes a strong lateral high electric field which is generated in a boundary between an "expansion region" of a high potential in the channel region (the "expansion region" has been generated by applying a voltage as high as 11 V to the source region 206) and an "inversion channel region" in a region immediately under the control gate 205. A phenomenon that channel hot electrons, which have obtained high energy by the lateral high electric field, are injected into the oxide film so as to reach the floating gate 203 is utilized. This data write operation is performed by exchanging the voltages to be applied to the source region 206 and the drain region 207 with each other. However, in the other respects, this operation is performed in the same way as the data write operation performed by the device shown in FIG. 23. In the device shown in FIG. 24, the injection efficiency is further increased by the thick source region 206 which is capacitively coupled to the floating gate 203.
The erasure of data is performed by taking out the electrons in the floating gate 203 into the control gate 205 by applying a voltage of about 14 V to the control gate 205 and by utilizing the FN tunneling phenomenon, thereby trying to improve the erasure characteristics. In the device shown in FIG. 24, the effective channel length is decreased by the thick source region 206 which is employed for increasing the capacitance coupling with the floating gate 203. Thus, this device is not appropriate for further reducing the size of a memory cell.
FIG. 25 shows the cross section of a nonvolatile semiconductor memory device which is designed to shorten a write time or to reduce a write voltage by increasing a write efficiency. This device is disclosed by Nakao, et al. in Japanese Laid-Open Publication No. 7-115142.
The device shown in FIG. 25 uses a semiconductor substrate 301 with a step 302 formed on the surface thereof. The surface of the semiconductor substrate 301 is divided by this step 302 into a surface at a relatively high level (first surface region) and a surface at a relatively low level (second surface region). A tunnel oxide film 303, a floating gate 304, a capacitive insulating film 305 and a control gate 306 are stacked in this order over the step 302. In the surface of the semiconductor substrate 301, a high-concentration source region 307 and a high-concentration drain region 308, both of which have been doped with an impurity at a high concentration, are formed. A thin high-concentration impurity layer (having a thickness of 0.1 .mu.m or less) 309 extends from the high-concentration drain region 308 along the sides of the step 302 to reach the first surface region. Since the thin high-concentration impurity layer 309 functions as a drain region, the region between the high-concentration source region 307 and the high-concentration impurity layer 309 becomes a channel region. The floating gate 304 is formed so as to overlap the channel region and to cover the high-concentration impurity layer 309.
In such a structure, since the floating gate 304 is located in the directions of the velocity vectors of channel hot electrons, the channel hot electron injection efficiency is presumably increased.
Next, a method for fabricating the nonvolatile semiconductor memory device shown in FIG. 25 will be described with reference to FIGS. 26A to 26E.
First, as shown in FIG. 26A, an oxide film 311 is formed as a mask for forming a step in the semiconductor substrate 301 made of p-type silicon. Thereafter, a part of the oxide film in the region where the step is to be formed is etched by a commonly used patterning technique. Then, the semiconductor substrate 301 is etched by using the oxide film 311 as a mask, thereby forming a step in the surface of the semiconductor substrate 301. Subsequently, As ions are implanted into the whole of the step side region and the second surface region at a relatively high dose of 1.0.times.10.sup.15 cm.sup.-2 and with an acceleration energy of 20 keV. This ion implantation is performed by a large-angle-tilt ion implantation technique in which the implantation angle is set at 30 degrees. As a result, as shown in FIG. 26B, the thin high-concentration impurity layer 309 is formed in the whole of the step side region and the second surface region. It is described in the above-cited document that the high-concentration impurity layer 309 thermally diffuses during the fabrication process and it is also described therein that the resulting thickness thereof after the fabrication process is completed becomes 0.05 .mu.m. Next, as shown in FIG. 26C, the oxide film 311 is removed and then the surface of the semiconductor substrate 301 is thermally oxidized, thereby forming the tunnel oxide film 303 as a first insulating layer so that the film has a thickness of 10 nm. Furthermore, CVD poly-silicon having a thickness of 200 nm is deposited thereon, thereby forming the floating gate 304. A second insulating film (thickness: 20 nm) 305 functioning as a capacitive insulating film is formed on the floating gate 304 by thermally oxidizing the surface of the floating gate 304. Thereafter, a CVD poly-silicon film having a thickness of 200 nm is deposited thereon, thereby forming the control gate 306.
The floating gate 304, the capacitive insulating film 305 and the control gate 306 are patterned as shown in FIG. 26D. And then, as shown in FIG. 26E, As ions are implanted into the semiconductor substrate 301 at a dose of 3.0.times.10.sup.15 cm.sup.-2 and with an acceleration energy of 50 keV, thereby forming the high-concentration source region 307 and the high-concentration drain region 308.
In the nonvolatile semiconductor memory device shown in FIG. 25, since the floating gate 304 is formed in the directions of the velocity vectors of channel hot electrons, the channel hot electron injection efficiency is allegedly increased. For such a purpose, a thin drain layer having a symmetric impurity concentration is formed as a high-concentration impurity layer so as to uniformly cover the step by implanting As ions by a large-angle-tilt ion implantation in which the implantation angle is set at 30 degrees, the acceleration energy is set at as low as 20 keV and the dose is set at 1.0.times.10.sup.15 cm.sup.-2. The resulting impurity concentration thereof reaches 1.0.times.10.sup.20 cm.sup.-3.
Since the devices shown in FIGS. 23 and 25 utilize the FN tunneling phenomenon for erasing data, abrupt band bending and a high electric field are generated at the edge of the drain region in the vicinity of the surface thereof, and the holes, which have been generated by the band-to-band tunneling current, are injected into the oxide film. As a result, a variation is caused in erasure characteristics and a retention margin and a write disturb margin are degraded. Particularly when data is erased from a large block, it takes a time 100 times or more as long as the time required for one-bit erasure. Thus, in a memory cell having a weak resistance, the retention margin is seriously degraded. In addition, even when the drain voltage is restricted to about 1.5 V for reading, it is still impossible to suppress the degradation of the read disturb margin.
In the device shown in FIG. 25, since the high-concentration drain layer reaches the surface of the upper part of the step, the electron injection efficiency cannot be increased and the variation in erasure characteristics and the degradation of the write disturb margin and the read disturb margin cannot be suppressed. The reasons thereof are as follows. At the edge of the high-concentration drain layer, a drain potential, which has been applied to the drain region in a corner portion in the upper part of the step, can be retained. However, the horizontal electric field intensity dramatically decreases in the high-concentration drain layer and the energy of hot electrons decreases in the interface with the semiconductor substrate in the step side region. Though some distance differential is generated by the non-equilibrium transportation between the position of the peak of electric field and the position of an average energy peak of electrons, the differential is approximately on the order of a mean free path. In a silicon crystal, the differential is about 10 nm. As the difference between the thickness of the thin drain layer and this value increases, the energy of electrons in the silicon interface in the step side region exponentially decreases so that the electron injection efficiency is decreased. That is to say, this structure requires an extremely thin drain layer. Furthermore, in the high-concentration drain layer, the hot electrons come into contact with the electrons in a thermal equilibrium state, thereby scattering the electrons, making the directions of the electron velocity vectors less aligned with the direction of the electric field and resulting in a decrease of the electron injection efficiency. Thus, for example, if the impurity concentration within the drain layer is symmetrically decreased so as to suppress the scattering of electrons within the drain layer, then the drain potential drops in the extremely thin drain layer formed along the side and the bottom of the step, the drain potential also drops in the corner portion in the upper part of the step and the horizontal electric field intensity decreases between the drain layer and the channel. As a result, the electron injection efficiency also decreases in the step side region.
Moreover, this structure cannot erase data by taking out electrons from the floating gate into the drain layer by utilizing the Fowler-Nordheim (FN) tunneling phenomenon. Since the high-concentration drain layer is in contact with the channel region, it is necessary, for example, to apply an electric field weakening diffusion layer surrounding the high-concentration drain region, in order to suppress the generation of the band-to-band tunneling current during erasure. However, in such a case, the electron injection efficiency is extremely decreased during writing, and such a structure cannot be fabricated at a very small size because of a short channel effect.
Furthermore, even when the drain voltage is restricted to about 1.5 V during reading, the read disturb margin is still degraded by the thin high-concentration drain layer.
An objective of the present invention is providing a nonvolatile semiconductor memory device which can remarkably increase an electron injection efficiency, thereby enabling a high-speed write operation and a low-power-consumption operation.
Another objective of the present invention is providing a nonvolatile semiconductor memory device suitable for very large-scale integration.
Still another objective of the present invention is to providing a nonvolatile semiconductor memory device which can erase data by taking out electrons from a floating gate into a control gate or a drain region.
Still another objective of the present invention is providing a nonvolatile semiconductor memory device which can improve the erasure characteristics by suppressing the injection of holes into an oxide film when data is erased.
Still another objective of the present invention is providing a nonvolatile semiconductor memory device which can suppress the degradation of a read disturb margin and which can increase a high-speed read ability.
Yet another objectives of the present invention are providing a method for fabricating the nonvolatile semiconductor memory device and providing a semiconductor integrated circuit device including such a nonvolatile semiconductor memory device.